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HIGHLIGHTS
porating all
of
these, the 80386 delivers the
highest perfonnance of any currently available
microprocessor.
The
80386
is
implemented in Intel's
CHMOS
III,
a semiconductor process that combines the high
frequency
of
HMOS
with the modest power
requirements of
CMOS. Using
1.5
microngeome-
tries and two metal layers, the
80386 packs over
275,000 transistors into a single chip. Both
12
and
16
MHz versions
of
the 80386 are initially
available; running without wait states, the
16
MHz
part can achieve sustained execution rates
of
34
million instructions per second.
Internally, the
80386
is
partitioned into six units
that operate autonomously and
in
parallel with
each other, synchronizing as necessary.
All
the
internal buses that connect these units are 32 bits
wide.
By
pipelining its functional units, the 80386
can overlap the execution
of
different stages
of
one instruction and can process multiple instruc-
tions simultaneously. Thus, while one instruction
is
executed, another
is
decoded, and a third
is
fetched from memory.
In addition to pipelining all instructions, the
80386 applies dedicated hardware to important
operations. The
80386's multiplyj divide unit can
perform 32-bit multiplication in
941 clocks,
depending on the number
of
significant digits; it
can divide 32-bit operands in
38
clocks (unsigned)
or
43
clocks (signed). The 80386's barrel shifter
can shift
1-64
bits in a single clock.
Many 32-bit applications, such as reprogram-
mabIe multiuser computers, need the logical-to-
physical address translation and protection pro-
vided
by
a memory management unit, or MMU.
Other applications, for example, embedded real-
time control systems, do not. Most 32-bit micro-
processor architectures respond to this dichotomy
by implementing the memory management unit
in an optional chip. The
80386 MMU, by
contrast,
is
incorporated
on
the processor chip as
two
of
the processor's pipelined functional units.
The operating system controls the operation
of
the MMU, allowing a real-time system, for
1-2
example, to forgo page translation. Implementing
memory management on-chip produces better
perfonnance for applications that use the
MMU
and no performance penalty for those that do
not. This achievement
is
made possible by
shorter signal propagation delays, use of the
half-clock cyles that are available on-chip, and
parallel operation.
Another facility that
is
crucial to some appli-
cations and irrelevant to others
is
"number
crunching,"
particularly single-
and
double-
precision floating point arithmetic. Floating
point operands are large, and the useful set of
operations on them
is
quite complex; many
thousands
of
transistors are required to imple-
ment a standard set
of
floating point operations
such as those defined by IEEE standard
754.
Consequently, the 80386 provides hardware sup-
port for numerics in a separate numeric coproces-
sor chip. In fact, either
of
two chips, the 80287
Numeric Coprocessor
or
the higher-perf onnance
80387,
can be connected to the 80386. The
numeric coprocessors are invisible to applica-
tion software; they effectively extend the
80386
architecture with IEEE 754-compatible regis-
ters, data types, and instructions. The combi-
nation of an
80386
and an
80387
can execute
1.8
million Whetstones per second.
A 32-bit processor running
at
16
Mhz can outrun
all but the fastest memories, making memory
access time a potential performance bottleneck.
The
80386 bus has been designed to make the
best use
of
both very fast static RAMs and
less
expensive dynamic RAMs.
For
accesses to fast
memory, such as caches, the
80386 provides a
two-clock address-to-data bus cycle.
(80386
caches can be any
size
from a minimum useful
capacity
of
4 kilobytes to the entire physical
address space.) Accesses to slower memories (or
Ij 0 devices) can utilize the 80386's address
pipelining facility to extend the effective address-
to-data time to three clocks, while maintaining
two-clock throughput to the processor. Because
of
its internal pipelining
of
address translation
with instruction execution, the
80386 generally