Filter
Top Products
inter
80386
5.4.3.3 NON·PIPELINED ADDRESS WITH
DYNAMIC DATA BUS SIZING
The physical data bus width for any non-pipelined
bus cycle can
be
either 32-bits or 16-bits. At the
beginning of the
bus
cycle, the processor behaves
as
if
the data bus
is
32-bits wide. When the
bus
cy-
cle
is
acknowledged, by asserting READY # at the
end of a
T2
state, the most recent sampling of
8S16# determines the data bus size for the cycle
being acknowledged. If
8S16#
was most recently
negated, the physical data bus size is defined
as
32
bits. If
8S16#
was most recently asserted, the
size is defined
as
16 bits.
When
8S
16
# is asserted
and
two 16-bit
bus
cycles
are required to complete the transfer,
8S16#
must
be
asserted during the second cycle; 16-bit bus size
is
not assumed. Like any
bus
cycle, the second 16-
bit
cycle must
be
acknowledged by asserting
READY#.
When a second 16-bit
bus
cycle
is
required to com-
plete the transfer over a 16-bit
bus,
the addresses
A
TRANSFER
REQUIRING
TWO
CYCLES
ON
16-BIT
DATA
BUS
A
TRANSFER
REQUIRING
TWO
CYCLES
ON
16-BIT
DATA
BUS
CLK2 [
(82384
CLK)
[
BEO#,BEl
#
[
BE2
# ,BE3 #
[
A2-
A31.
M/IO#.D/C#
W/R#
[
ADS
#
[
NA#
[
BS16 # [
READY
#
[
LOCK#
[
00-
015
[
IDLE
Ti
CYCLE
1
tCYCLE
1 A
NON-PIPELINED NON-PIPELINED
(WRITE
WRITE)
PART
ONE
PART
TWO
T1
T2
T1
T2
CYCLE
2
TCYCLE
2A
NON-PIPELINED NON-PIPELINED
(READ
READ)
PART
ONE
PART
TWO
T1
T2
T1
T2
IDLE
Ti
016-031
[ •
-------<:t==~O~U~T~==t=)
IGNORED IGNORED
--0--
---0---
Key:
Dn
~
physical data pin n
dn
~
logical data bit n
I I
Figure 5·14; Asserting BS16# (zero wait states, non·pipelined address)
78
231630-18