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TABLE OF CONTENTS
BOOK I
CHAPTER 1
HIGHLIGHTS
1.1
32-bit Architectu
re
..............................................................
1-1
1.2
High-performance Implementation
...............................................
1-1
1.3
Virtual Memory Support
........................................................
1~3
1.4
Configurable Protection
........................................................
1-3
1.5
Extended Debugging Support
...................................................
1-3
1.6
Object Code Compatibility
......................................................
1-4
1.7
Summary
.....................................................................
1-4
CHAPTER 2
APPLICATION ARCHITECTURIE
2.1
Registers
......................................................................
2-1
2.1.1
General Registers
...........................................................
2-1
2.1.2
Flags and Instruction Pointer
.................................................
2-1
2.1.3
Numeric Coprocessor Registers
..............................................
2-2
2.2 Memory and
Logical Addressing
.................................................
2-3
2.2.1
Segments
..................................................................
2-3
2.2.2
Logical Addresses
..........................................................
2-3
2.2.3
Segment and Descriptor Registers
............................................
2-4
2.2.4 Addressing Modes
..........................................................
2-5
2.3
Data Types and Instructions
.....................................................
2-6
2.3.1
Principal Data Types
........................................................
2-6
2.3.2 Numeric Coprocessor Data Types
............................................
2-7
2.3.3
Other Instructions
..........................................................
2-7
2.3.3.1
Stack Instructions
.......................................................
2-7
2.3.3.2 Control Transfer Instructions
.............................................
2-8
2.3.3.3
Miscellaneous Instructions
...............................................
2-10
CHAPTER 3
SYSTEM ARCHITECTURE
3.1
System Registers
...............................................................
3-1
3.2 Multitasking
...................................................................
3-1
3.2.1
Task State Segment
.........................................................
3-2
3.2.2
Task
Switching
.............................................................
3-2
3.3 Addressing
....................................................................
3-3
3.3.1
Address Translation Overview
................................................
3-3
3.3.2 Segments
.................................................................
3-4
3.3.3 Pages
.....................................................................
3-7
3.3.4 Virtual Memory
.............................................................
3-8
iii