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CLK2
[
BEO#-BE3#.
[
LOCK#
W/R#.M/IO#.
[
D/C#.ADS#
A2-A31
[
DO-D31 [
HLDA
[
80386
Th
Ti
OR
T1
@
ALSO
APPLIES
TO
DATA
FLOAT
WHEN
WRITE
CYCLE
IS
FOLLOWED
BY
READ
OR
IDLE
MAX
Figure 7·6. Output Float Delay and HLDA Valid Delay Timing
-RESET--I~'----INITIALIZATION
SEQUENCE
----
CLK2 [
RESET
[
The second internal processor phase following RESET high-Io-Iow transilion (provided
t25
and
t26
are met) is
4>2.
Figure 7·7. RESET Setup and Hold Timing, and Internal Phase
107
'J
MAX
231630-42
231630-43