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80386
NOTE:
CLK2[
(82384
ClK)
[
HOLD
[
HLDA
[
BEO#-BE3#,
A2-A31,
[
M/IO#, D/C#, W
/R#
ADS#
[
T1
CYCLE
1
NON-PIPELINED
(READ)
T2
T2
NOTE:
IF
ASSERTING
BS
16#
REQUIRES
A
SECOND
BUS
CYCLE
TO
BE
PERFORMED,
THE
SECOND
CYCLE
IS
PERFORMED
BEFORE
HOLD
ACKNOWLEDGE
HOLD
CYCLE
2
ACKNOWLEDGE
NON-PIPELINED
(WRITE)
Th
Th
T1
T2
VALID
2
OUT
231630-30
HOLD
is a synchronous input and can
be
asserted at any CLK2 edge, provided setup and hold
(t23
and
t24)
require-
ments are met. This waveform is useful for determining Hold Acknowledge latency.
Figure 5-26. Requesting Hold from Active Bus (NA # negated)
Provided the RESET falling edge meets setup and
hold times
t25
and
t26,
the internal processor clock
phase
is
defined at that time, as illustrated by Figure
5-28 and Figure
7-7.
An
80386 self-test may
be
requested at the time
RE-
SET
is
negated by having the BUSY # input at a
LOW
level,
as
shown
in
Figure 5-28. The self-test
requires
(2
20
) + approximately
60
CLK2 periods to
complete. The self-test duration
is
not affected by
the test results.
Even
if the self-test indicates a prob-
lem, the 80386 attempts to proceed with the reset
sequence afterwards.
90
After the RESET falling edge
(and
after the self-test
if it was requested) the
80386 performs
an
internal
initialization sequence for approximately 350 to 450
CLK2 periods.
Also during the initialization, between
the 20th CLK2 period and the first bus
cycle, the
ERROR # input
is
sampled to determine the pres-
ence of
an
80387 coprocessor versus the presence
of
an
80287 (or no coprocessor). To distinguish be-
tween
an
80287 being present and
no
coprocessor
being present requires a software test.