Filter
Top Products
SYSTEM ARCHITECTURE
Thble
3-1.,
Exceptions
ID
Description
0
Divide
Error
Debug Exception
3
Software Breakpoint
4 Overflow
5
Array Bound Check
6 Invalid Opcode
7
Coprocessor
Not
Present
8
Double
Fault
10
Invalid TSS
11
Segment
Fault
12
Stack
Under/ Overflow
13
General Protection Violation
14
Page
Fault
16
Coprocessor
Error
3.6.1.
Interrupt Descriptor Table
Having generated
or
obtained
an
interrupt
or
exception number, the 80386 uses the number
as
an
index into the
Interrupt
Descriptor
Table,
or
IDT. The
IDT
may be located
anywhere in memory; the operating system
initializes the
IDT
and loads its address into
the processor's
Interrupt
Descriptor Table
Register (IDTR). Like the
GDT
or
an
LDT,
the
IDT
is
a vector
of
descriptors, although
gates are the only type
of
descriptors allowed
in the IDT. There
is
one gate
in
the
IDT
for
each interrupt
and
exception handler. (The
IDT
is
functionally similar to the "interrupt
vector table" provided by a number
of
archi-
tectures.)
An
80386 interrupt
or
exception handler can
be implemented as a procedure
or
a task; the
merits
of
these two alternatives are discussed
shortly.
The
80386 invokes a procedure-based
handler
much
as it performs a gated system
call.
To
invoke a task-based handler, the 80386
performs a
task
switch. A handler's
IDT
gate
type tells the processor how to invoke the
handler (see Table 3-2). As mentioned,
inter-
rupt
and
trap
gates are functionally similar to
call gates, except
that
they have
no
provision
for copying parameters, and they also cause
the 80386
to
save the Flags register
on
the
handler's stack. They differ from one
another
only in the state
of
the
Interrupt
Enable
Flag
(IF)
at
entry to the handler;
an
interrupt
handler
is
entered with interrupts disabled,
while
a trap handler, which
is
typically used to
handle exceptions,
is
entered with interrupts
unchanged.
As
part of switching to a task-based
handler, the 80386 loads the Flags register
with the value saved in the task's TSS, allowing
the handler to run with interrupts enabled
or
disabled.
Table 3-2.
Interrupt
and Exception
Gate Characteristics
Gate Type
Handler
Interrupts
Interrupt Procedure
Disabled
Trap Procedure Enabled
Task Task
(Handler's
IF
Flag)
Procedure-based handlers are appropriate for
routines that should run in the context (that
is,
use the address space and register values)
of
the
task that
is
interrupted
or
incurs the exception.
At
16
MHz, the invocation sequence takes 3.6
microseconds. Like any other procedure, an
interrupt
or
exception procedure has access to all
of
the running task's
resources-its
data and
code, its registers, and its stack. This
is
as it
should be for most exceptions, because a task
causes
an
exception and ready access to task data
may be required to resolve
it.
For
example, a
page fault handler needs the running task's page
tables to find the not-present page's disk address.
3-15