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80386
Table 8·1 80386
Instruction
Set
Clock
Count
Summary (Continued)
CLOCK COUNT NOTES
Real
Real
INSTRUCTION FORMAT
Address Protected
Address
Protected
Mode
or
Virtual Mode
or
Virtual
Virtual
Address
Virtual Address
8086 Mode
8086
Mode
Mode
Mode
ARITHMETIC (Continued)
DIV
~
Divide (Unsigned)
Accumulator
by
Register/Memory
I
11
11011
w Imod 11 0
r/ml
Divisor-Byte
14/17
14/17
b,o
e,h
-Word
22/25
22/25
b,e
e,h
-Doubleword
38/41
38/41
b,e
e,h
IDIV
~
Integer
Divide (Signed)
Accumulator By
Register/Memory
I
1111011
w Imod
111
r/ml
Divisor-Byte
19/22
19/22
b,e
e,h
-Word
27/30 27/30
b,e e,h
-Doubleword
43/46 43/46
b,e
e,h
AAD
~
ASCII
Adjust
for
Divide
I
11010101
I
00001010
I
19
19
AAM
~
ASCII
Adjust
for
Multiply
I
11010100
I
00001010
I
17
17
CBW = Convert Byte to Word
I
100110001
3 3
CWO
~
Convert
Word
to
Double
Word
I
10011001
I
2
2
LOGIC
Shift Rotate Instructions
Not Through Carry (ROL, ROR, SAL, SAR, SHL, and SHR)
Register/Memory by 1
11101
OOOw
ImOdTTT
r/ml
317
317 b
h
RegisterlMemory by
CL
11101001
w I
mod
TIT
r/ml
3/7
3/7
b
h
Register/Memory
by
Immediate Count
I
11
OOOOOw I mod
TIT
r/mlimmed 8·bit data
3/7
317 b
h
Through Carry (RCL and RCR)
Register/Memory
by
1
I
1101
OOOw
ImOdTIT
r/ml
9/10
9/10
b
h
RegisterlMemory by
CL
I
1101001
w I mod
TIT
r/ml
9/10
9/10
b
h
RegisterlMemory
by
Immediate Count
11
1
00000
w I
mod
TIT
r/ml
immed B·bit data
9/10
9/10
b
h
TTT
Instruction
000
ROL
001
ROR
010
RCL
011
RCR
100
SHL/SAL
101
SHR
111
SAR
SHLD
~
Shift
Left
Double
Register/Memory
by
Immediate
I
00001111
I
1
01
001
00
Imod
reg
r/mlimmed S-bit data
3/7 3/7
RegisterlMemory
by
CL
I
00001111
I
10100101
ImOdreg
r/ml
317
3/7
SHRD
~
Shift
Right Double
Register/Memory
by
Immediate
I
00001111
I
10101100
ImOd
reg
r/ml
immed B·bit data
3/7
317
RegisterlMemory by CL
I
0000111
1
I
10101101
ImOd
reg
r/ml
3/7
317
AND
~
And
Register to Register
I
001000
d w Imod reg
r/ml
2 2
114