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80386
At the end of the second bus state within the bus
cycle, READY # is sampled. At that time, if external
hardware acknowledges the bus cycle by asserting
READY
#,
the bus cycle terminates as shown
in
Fig-
ure 5-11. If READY #
is
negated as
in
Figure 5-12,
the
cycle continues another bus state
(a
wait state)
and READY # is
sampled again at the end of that
state. This continues
indefinitely until the cycle
is
ac-
knowledged
by READY # asserted.
When the current
cycle
is
acknowledged, the 80386
terminates it. When a read cycle is acknowledged,
the 80386 latches the information present at its data
pins. When a write
cycle is acknowledged, the
80386 write data remains valid throughout phase
one
of
the next bus state, to provide write data hold
time.
5.4.3.2
NON-PIPELINED ADDRESS
Any bus
cycle may
be
performed with non-pipelined
address timing. For example, Figure
5-11
shows a
mixture of read and write
cycles with non-pipe lined
address timing. Figure
5-11
shows the fastest possi-
ble cycles
with non-pipelined address have two bus
states per bus
cycle. The states are named
T1
and
T2.
In
phase one of the T1, the address signals and
bus
cycle definition signals are driven valid, and to
signal their availability, address status (ADS#) is
simultaneously asserted.
During read or write
cycles, the data bus behaves as
follows. If the cycle is a read, the 80386 floats its
data
signals to allow driving by the external device
being addressed.
If the cycle is a write, data signals
are
driven by the 80386 beginning
in
phase two of
T1
until phase one of the bus state following cycle
acknowledgment.
Figure 5-12 illustrates
non-pipelined bus cycles with
one wait added to
cycles 2 and
3.
READY#
is
sam-
pled
negated at the end of the first T2
in
cycles 2
and
3.
Therefore cycles 2 and 3 have T2 repeated.
At the end of the second T2, READY #
is
sampled
asserted.
IDLE
I
CYCLE
1 I
NON-PIPElINED
(READ)
CYCLE
2
NON-PIPELINED
(WRITE)
CYCLE
3
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(READ)
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T2
T1
T2
T2
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T2 T2
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231630-16
Idle states are shown here for diagram variety only. Write cycles are
not
always followed by an idle state. An active bus cycle can immediately
follow
the write cycle.
Figure 5·12. Various Bus Cycles and Idle States
with
Non-Pipelined
Address
(various
number
of
wait
states)
76