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80386
Address bits
AO
and
A1
of the physical operand's
base address can
be
created when necessary (for
instance, for Multibus
I
or
Multibus
II
interface),
as
a
function of the lowest-order asserted Byte Enable.
This
is
shown
by
Table 5-6. Logic to generate
AO
and A 1
is
given
by
Figure
5-3.
Table 5-5. Byte Enables and
Associated
Data and Operand
Bytes
Byte
Enable Signal
Associated
Data
Bus
Signals
BEO#
00-07
(byte
O-Ieast
significant)
BE1#
08-015
(byte
1)
BE2#
016-023
(byte
2)
BE3#
024-031
(byte
3-most
significant)
BEO#
L H
L x
(HI
L
L
L
A31
A31
A31
A31
A31
A31
Table 5-6. Generating AO-A31
from
BEO#-BE3#
and
A2-A31
80386
Address
Signals
.........
A2
BE3#
BE2#
BE1#
Physical Base
Address
"
.......
A2
A1
AO
.........
A2 0 0 X
X
X
.......
,'
A2 0
1 X X Low
.........
A2 1
0 X Low
High
.........
A2 1
1 Low High High
L x
BE2#
L L
H
H
L
x
L
H
BEO#
~~
BE3#~
x x
H)
x L
L
H L
BE1#
231630-3
K - Map for A 1 Signal
BEO#
L H
L x L H L
L
L
x L H
H
L
L
x H
BE2#
BE3#
H
x x H x L
L
H L
BE1#
231630-4
K - Map for
AO
Signal
BEO#
Low
High
High
High
Figure 5-3.
Logic
to
Generate
AO,
A1
from
BEO#-BE3#
Each bus cycle
is
composed of at least two
bus
states. Each bus state requires one processor clock
period. Additional bus states added to a single bus
cycle are called wait states. See 5.4
Bus
Functional
Description.
Since a bus cycle requires a minimum of two bus
states (equal to two processor clock periods), data
can be transferred between external devices and
the 80386 at a maximum rate of one 4-byte Dword
every two processor clock periods, for a maximum
bus bandwidth of
32
megabytes/second (80386-16
operating at 16 MHz processor clock rate).
67
5.3.2
Memory
and
1/0
Spaces
Bus cycles may access physical memory space or
I/O
space. Peripheral devices in the system may ei-
ther be memory-mapped,
or
I/O-mapped, or both.
As shown
in
Figure
5-4,
physical memory addresses
range from
OOOOOOOOH
to FFFFFFFFH
(4
gigabytes)
and
I/O
addresses from
OOOOOOOOH
to
OOOOFFFFH
(64 kilobytes) for programmed I/O. Note the
I/O
ad-
dresses used
by
the automatic
I/O
cycles for co-
processor communication are
800000F8H to
800000FFH, beyond the address range of pro-
grammed
I/O, to allow easy generation of a coproc-
essor chip select signal using the
A31
and
M/IO#
Signals.