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80386
RWi
(memory access qualifier bits)
A 2-bit RW
field exists for each of the four break-
points. The 2-bit RW
field specifies the type of usage
which must occur
in
order to activate the associated
breakpoint.
RW
Usage
Encoding Causing Breakpoint
00 Instruction execution only
01
Data writes only
10
Undefined-do
not use this encoding
11
Data reads and writes only
RW
encoding 00 is used to set up an instruction
execution breakpoint. RW encodings
01
or
11
are
used to set up
write-only or read/write data break-
points.
Note that
instruction execution breakpoints are
taken
as
faults (i.e. before the instruction exe-
cutes), but
data breakpoints are taken as traps
(i.e. after the data transfer takes place).
Using LENi and RWi to Set Data Breakpoint i
A data breakpoint can
be
set up by writing the linear
address into DRi
(i
=
0-3).
For data breakpoints,
RWi
can =
01
(write-only) or
11
(write/read). LEN
can =
00,01,
or 11.
If a data access entirely or partly falls within the data
breakpoint
field, the data breakpoint condition has
occurred, and if the breakpoint is enabled, an excep-
tion 1 trap
will occur.
Using LENi and RWi to
Set Instruction Execution
Breakpoint i
An instruction execution breakpoint can be set up by
writing address of the beginning of the instruction
(including prefixes if any) into DRi
(i
=
0-3).
RWi
must
= 00 and LEN must = 00 for instruction exe-
cution breakpoints.
If the instruction beginning at the breakpoint address
is about to be executed, the instruction execution
breakpoint condition has occurred, and if the break-
point is
enabled,
an
exception 1 fault will occur be-
fore the instruction is executed.
Note that an instruction execution breakpoint ad-
dress must be
equal to the beginning byte address
of
an
instruction (including prefixes)
in
order for the
instruction execution breakpoint to occur.
GD
(Global Debug Register access detect)
The Debug Registers can
only
be
accessed
in
Real
Mode or at privilege level 0
in
Protected Mode. The
30
GD bit, when set, provides extra protection against
any
Debug Register access even in Real Mode or at
privilege level 0
in
Protected Mode. This additional
protection feature is provided to guarantee that a
software debugger (or
ICE-386) can have full control
over the Debug Register resources when required.
The GD bit, when set, causes an exception 1
fault if
an instruction attempts to read or write any Debug
Register. The GD bit is then automatically
cleared
when the exception 1 handler is invoked, allowing
the exception 1 handler free access to the debug
registers.
GE and
LE
(Exact data breakpoint match, global and
local)
If
either GE or
LE
is set, any data breakpoint trap will
be reported exactly after completion of the instruc-
tion that caused the operand transfer. Exact report-
ing
is
provided by forcing the 80386 execution unit to
wait for completion of data operand transfers before
beginning execution
of
the next instruction.
If exact data breakpoint match is not selected, data
breakpoints may not be reported until several in-
structions
later or may not be reported at all. When
enabling a data breakpoint, it is therefore recom-
mended to enable the exact data breakpoint match.
When the 80386 performs a task switch, the
LE
bit is
cleared. Thus, the
LE
bit supports fast task switching
out of tasks, that have enabled the exact data break-
point match for their
task-local breakpoints. The
LE
bit is cleared by the processor during a task switch,
to avoid having exact data breakpoint match en-
abled
in
the new task. Note that exact data break-
point match must
be
re-enabled under software con-
trol.
The 80386 GE bit is unaffected during a task switch.
The GE bit supports exact data breakpoint match
that is to remain
enabled during all tasks executing
in the system.
Note that
instruction execution breakpoints are al-
ways reported exactly, whether or not exact data
breakpoint match is
selected.
Gi
and
Li
(breakpoint enable, global and local)
If
either
Gi
or
Li
is set then the associated breakpoint
(as defined by the
linear address
in
DRi, the length
in
LENi and the usage criteria
in
RWi) is enabled. If
either
Gi
or
Li
is set, and the 80386 detects the ith
breakpoint condition, then the exception 1
handler
is
invoked.
When the 80386 performs a task switch to a new
TSS, all
Li
bits are cleared. Thus, the
Li
bits support
fast task switching out of tasks that use some task-
local breakpoint registers. The
Li
bits are cleared by