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CLK2
[
READY#
[
HOLD
[
DO-D31
[
(INPUT)
BU5Y#.
[
ERROR#
PEREQ
NA#
[
B516#
[
INTR.
[
NMI
CLK2
[
8EO#-8E3#.
[
LOCK#
W!R#.M!IO#.
[
O!C#.AOS#
A2-A31
[
00-031
[
(OUTPUT)
HLOA
[
80386
Tx Tx
~2
Figure 7·4. Input Setup and Hold Timing
Tx
Figure 7·5. Output Valid Delay Timing
106
Tx
231630-40
231630-41