Filter
Top Products
inter
80386
NA#'
(PIN
013)
D--4
NA#
(INTERNAL)
9S16#
c:_
.....
----
9S16 #
(PIN C14)
(INTERNAL)
231630-22
Figure 5-18. 80386 Internal
Logic on
NA#
and
8516#
The complete bus state transition diagram, including
operation with pipelined address
is
given by 5-20.
Note it
is
a superset of the diagram for non-pipelined
address only, and the three additional bus states for
pipelined address are drawn
in
bold.
The fastest bus
cycle with pipelined address con-
sists of just two bus states,
T1
P and T2P (recall for
non-pipelined address it is
T1
and T2).
T1
P is the
first bus state of a pipelined
cycle.
5.4.3.5 INITIATING AND MAINTAINING
PIPELINED ADDRESS
Using the state diagram Figure 5-20, observe the
transitions from an idle state,
Ti,
to the beginning of
a pipelined bus
cycle,
T1
P.
From
an
idle state Ti, the
first
bus
cycle must begin with
T1,
and
is
therefore a
non-pipelined bus
cycle. The next bus cycle
Will
be
pipelined, however, provided
NA#
is asserted and
the first bus
cycle ends
in
a T2P state (the address
for the next bus
cycle
is
driven during T2P). The fast-
est path from
an
idle state to a bus cycle with pipe-
lined address
is
shown
in
bold below:
~
,T1-T~-T2P'J
,T1P:T2P'J
idle non-pipelined pipelined
states
cycle cycle
T1-T2-T2P are the states of the bus cycle that es-
tablishes address pipelining for the next bus cycle,
which begins with
T1
P.
The same
is
true after a bus
hold state, shown below:
,Th, Th,
Th')l..T1
- T2 - T2P'J ,T1 P - T2P'J
T
'f'
T
hold non-pipelined
acknowledge
cycle
states
pipelined
cycle
82
The transition to pipelined address is shown func-
tionally by Figure 5-17 Cycle
1.
Note that Cycle 1
is
used to transition into pipelined address timing for
the subsequent Cycles
2,
3 and
4,
which are pipe-
lined. The
NA#
input
is
asserted at the appropriate
time to select address pipelining for Cycles
2,
3 and
4.
Once a bus cycle is
in
progress and the current ad-
dress has been valid for one entire bus state, the
NA#
input
is
sampled at the end of every phase one
until the bus
cycle
is
acknowledged. During Figure
5-
17 Cycle 1 therefore, sampling begins
in
T2.
Once
NA#
is
sampled asserted during the current cycle,
the 80386 is free to drive a new address and bus
cycle definition on the bus as early as the next bus
state.
In
Figure 5-16 Cycle 1 for example, the next
address
is
driven during state T2P. Thus Cycle 1
makes the transition to pipelined address timing,
since it begins with
T1
but ends with
T2P.
Because
the address for Cycle 2 is available before Cycle 2
begins, Cycle 2
is
called a pipelined bus cycle, and it
begins with
T1
P.
Cycle 2 begins as soon as
READY # asserted terminates Cycle
1.
Example transition bus cycles are Figure 5-17 Cycle
1 and Figure 5-16 Cycle
2.
Figure 5-17 shows tran-
sition during the very first cycle after
an
idle bus
state, which
is
the fastest possible transition into ad-
dress pipelining. Figure 5-16 Cycle 2 shows a tran-
sition cycle occurring during a burst of bus cycles.
In
any case, a transition cycle is the same whenever it
occurs: it consists at least of T1, T2
(you
assert
NA#
at that time), and T2P (provided the 80386 has
an
internal bus request already pending, which it al-
most always has). T2P states are repeated if wait
states are added to the
cycle.
Note three states
(T1,
T2 and T2P) are only required
in
a bus cycle performing a transition from non-
pipelined address into pipelined address timing, for
example Figure 5-17 Cycle
1.
Figure 5-17 Cycles
2,
3 and 4 show that address pipelining can
be
main-
tained with two-state bus cycles consisting only of
T1P and
T2P.
Once a pipelined bus cycle is
in
progress, pipelined
timing
is
maintained for the next cycle by asserting
NA#
and detecting that the 80386 enters T2P dur-
ing
the current bus cycle. The current bus cycle must
end
in
state T2P for pipelining to be maintained
in
the next cycle. T2P
is
identified by the assertion of
ADS#.
Figures 5-16 and 5-17 however, each show
pipelining ending after Cycle
4 because Cycle 4
ends
in
T21.
This indicates the 80386 didn't have
an
internal bus request prior to the acknowledgement
of Cycle
4.
If a cycle ends with a T2 or
T21,
the next
cycle will not
be
pipelined.