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80386
CYCLE
1 I
NON-PIPELINED
(WRITE)
T1
T2
CYCLE
2 I
NON-PIPELINED
(HALT)
T1
T2
IDLE
Ti
Ti
Ti Ti
CLK2 [
(82384
CLK) [
BEO~
BEl"
BE3"[
MilO"
W/R#
'rr-:":,~:-:--+:,-+---bV'\.ml::7o;",,od-
80386
REMAINS
HAL
TED
UNTIL
INTR,
NMI
OR
~"-lo"-..lj'-l"-lo"-~t-
RESET
IS
ASSERTED.
I I
BE2#,
A2-A31,
[
O/C#
""",",,~-""'i"'--+a;..;..;....;,,;+...;.;..;;,.;,;;f->'~~f->"~"-t-
80386
RESPONDS
TO
ADS#[
NA#[
READY#
[
LOCK#[
00-031
[
,
---i---t---t-
HOLD
INPUT
WHILE
IN
THE
HALT
STATE.
- (FLOATING) - -
--
I I
231630-27
Figure 5-23. Halt Indication Cycle
The LOCK # output
is
asserted from the beginning
of the first interrupt
acknowledge cycle until the end
of the second interrupt
acknowledge cycle. Four idle
bus states,
Ti,
are inserted
by
the 80386 between
the two interrupt
acknowledge cycles, allowing at
least 160
ns
of locked idle time for future 80386
speed
selections
up
to 24 MHz (CLK2
up
to 48
MHz),
for compatibility with spec TRHRL of the
8259A
Interrupt Controller.
During both interrupt
acknowledge cycles,
00-031
float. No data
is
read at the end of the first interrupt
acknowledge cycle. At the end of the second inter-
rupt acknowledge cycle, the 80386 will read
an
ex-
ternal
interrupt vector from
00-07
of the data bus.
The vector indicates the specific interrupt number
(from
0-255)
requiring service.
87
5.4.5 Halt Indication Cycle
The 80386 halts as a result of executing a HALT
instruction.
Signaling its entrance into the halt state,
a
halt indication cycle
is
performed. The halt indica-
tion
cycle
is
identified
by
the state of the bus defini-
tion
signals shown
in
5.2.5
Bus
Cycle Definition
and a byte address of
2.
BEO# and
BE2#
are the
only signals distinguishing halt indication from shut-
down indication, which drives
an
address of
O.
Dur-
ing
the halt cycle undefined data is driven
on
00-031.
The halt indication cycle must be acknowl-
edged by READY # asserted.
A
halted 80386 resumes execution when INTR
(if
interrupts are enabled) or
NMI
or
RESET
is
assert-
ed.