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80386
15 0
BACK
LINK
SELECTOR
TO
TSS
SP
FOR
CPL
0
SS
FOR
CPL
0
SP
FOR
CPL
1
SS
FOR
CPL
1
SP
FOR
CPL
2
SS
FOR
CPL
2
IP
(ENTRY
POINT)
FLAGS
AX
CX
OX
BX
SP
BP
SI
01
ES
SELECTOR
CS
SELECTOR
SS
SELECTOR
OS
SELECTOR
TASK'S
LOT
SELECTOR
AVAILABLE
,
o
2
4
6
INITIAL
STACKS
8
FOR
CPL
0,1,2
A
C
E
10
12
14
16
18
CURRENT
1A
TASK
IC
STATE
IE
20
22
24
26
28
2A
231630-65
Figure 4·16. 286 TSS
When
a GALL or INT instruction initiates a task
switch, the new
TSS
will
be
marked busy and the
back
link field of the new TSS set to the old
TSS
selector. The
NT
bit of the new task
is
set by GALL
or
INT
initiated task switches.
An
interrupt that does
not cause a task switch
will clear
NT.
(The
NT
bit will
be restored after execution of the interrupt handler)
NT may also
be
set or cleared by POPF or IRET
instructions.
The 386 task state segment
is
marked busy
by
changing the descriptor type field from TYPE
9H
to
TYPE
BH.
A 286
TSS
is
marked busy
by
changing
the descriptor type
field from TYPE 1 to TYPE
3.
Use of a selector that references a busy task state
segment causes
an
exception
13.
The Virtual Mode
(VM)
bit 17
is
used to indicate if a
task,
is
a virtual 8086 task.
If
VM
=
1,
then the tasks
will
use
the Real Mode addressing mechanism. The
virtual 8086 environment
is
only entered and exited
via a task switch (see section 4.6
Virtual Mode).
The coprocessor's state
is
not automatically saved
when a task switch occurs, because the incoming
50
task may not use the coprocessor. The Task
Switched
(TS)
Bit (bit 3
in
the
GRO)
helps deal with
the coprocessor's state
in
a multi-tasking environ-
ment. Whenever the
80386 switches tasks, it sets
the
TS
bit. The 80386 detects the first use of a proc-
essor extension instruction after a task switch and
causes the processor extension not
available excep-
tion
7.
The exception handler for exception 7 may
then decide whether to save the state of the co-
processor. A processor extension not present ex-
ception
(7)
will occur when attempting to execute an
ESG
or WAIT instruction if the Task Switched and
Monitor coprocessor extension bits are both set
(i.e.
TS
= 1 and
MP
=
1).
The T bit
in
the 386
TSS
indicates that the processor
should generate a debug exception when switching
to a task.
If T = 1 then upon entry to a new task a
debug exception 1
will
be
generated.
4.4.7 Initialization and Transition
to
Protected
Mode
Since the 80386 begins executing
in
Real Mode
im-
mediately after RESET it
is
necessary to initialize the
system
tables and registers with the appropriate val-
ues.
The GOT and lOT registers must refer to a valid GOT
and
lOT.
The
lOT
should
be
at least 256 bytes long,
and GOT must contain descriptors for the initial
code, and data segments. Figure 4-17 shows the
tables and Figure 4-18 the descriptors needed for a
simple Protected Mode 80386 system.
It
has a sin-
gle code and single data/stack segment each four
gigabytes
long and a single privilege level
PL
=
O.
The actual method of enabling Protected Mode
is
to
load
GRO
with the
PE
bit set, via the
MOV
GRO,
R/M
instruction. This puts the 80386
in
Protected Mode.
After
enabling Protected Mode, the next instruction
should execute an intersegment JMP to load the
GS
register and flush the instruction decode queue. The
final step
is
to load all of the data segment registers
with the
initial selector values.
An
alternate approach to entering Protected Mode
which
is
especially appropriate for multi-tasking op-
erating systems,
is
to use the built
in
task-switch to
load all of the registers.
In
this case the GOT would
contain two
TSS
descriptors
in
addition to the code
and data descriptors needed for the first task. The
first
JMP instruction
in
Protected Mode would jump
to the
TSS causing a task switch and loading all of
the registers with the
values stored
in
the
TSS.
The
Task
State Segment Register should
be
initialized to
point to a
valid TSS descriptor since a task switch
saves the state of the current task
in
a task state
segment.