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80386
Table 5-2 Bus
Cycle
Definition
MIIO#
D/C#
W/R#
Bus
Cycle
Type
Locked?
Low
Low Low
INTERRUPT ACKNOWLEDGE Yes
Low Low High does not occur
Low
High
Low
1/0
DATA READ
No
Low
High
High
I/O
DATA WRITE
No
High
Low
Low
MEMORY CODE READ
No
High Low High HALT:
SHUTDOWN: No
Address
= 2
Address
= 0
(BEO#
High
(BEO# Low
BE1
# High
BE1
# High
BE2#
Low
BE2#
High
BE3#
High
BE3#
High
A2-A31 Low) A2-A31 Low)
High High Low
MEMORY DATA READ Some Cycles
High High High
MEMORY DATA WRITE
Some
Cycles
5.2.6 Bus
Control
Signals
5.2.6.1 INTRODUCTION
The following signals allow the processor to indicate
when a bus cycle has begun, and
allow other system
hardware to control address pipelining, data bus
width and bus cycle termination.
5.2.6.2 ADDRESS STATUS
(ADS#)
This three-state output indicates that a valid bus cy-
cle
definition, and address
(W/R#,
D/C#,
M/IO#,
BEO#-BE3#,
and
A2-A31)
is
being driven at the
80386 pins.
It
is
asserted during
T1
and T2P bus
states (see 5.4.3.2
Non-pipelined
Address
and
5.4.3.4
Pipelined
Address
for additional information
on
bus states).
5.2.6.3 TRANSFER ACKNOWLEDGE (READY#)
This input indicates the current bus
cycle
is
com-
plete,
and the active bytes indicated
by
BEO
#-
BE3#
and BS16# are accepted or provided. When
READY #
is
sampled asserted during a read cycle or
interrupt acknowledge
cycle, the 80386 latches the
input data and terminates the
cycle. When READY #
is
sampled asserted during a write cycle, the proces-
sor terminates the bus cycle.
READY #
is
ignored on the first bus state of all bus
cycles, and sampled each bus state thereafter until
asserted. READY # must
eventually be asserted to
acknowledge every bus
cycle, including Halt Indica-
tion
and
Shutdown Indication bus cycles. When be-
63
ing sampled, READY must always meet setup and
hold times
t19
and
t20
for correct operation. See all
sections of 5.4
Bus
Functional Description.
5.2.6.4
NEKT ADDRESS REQUEST
(NA#)
This
is
used to request address pipelining. This input
indicates the system
is
prepared to accept new val-
ues of
BEO#-BE3#,
A2-A31,
W/R#,
D/C#
and
M/IO#
from the 80386 even if the end of the current
cycle is not being acknowledged
on
READY
#.
If th!s
input
is
asserted when sampled, the next address IS
driven onto the bus, provided the next bus request IS
already pending internally. See 5.4.2
Address
Pipe-
lining
and 5.4.3 Read and Write Cycles.
5.2.6.5 BUS SIZE
16
(BS16#)
The
BS16#
feature allows the 80386 to directly con-
nect to 32-bit and 16-bit data buses. Asserting this
input constrains the current bus cycle to use
only the
lower-order
half
(00-015)
of the data bus, corre-
sponding to BEO# and
BE1
#.
Asserting
BS16#
has
no additional effect if
only BEO#
and/or
BE1
# are
asserted
in
the current cycle. However, during bus
cycles asserting BE2# or BE3#, asserting
BS~6#
will automatically cause the
80386.
to make
adJust-
ments for correct transfer of the upper bytes(s) using
only physical data signals DO-D15.
If the operand spans both halves of the data bus
and
BS 16 #
is
asserted, the 80386 will automatically
perform another 16-bit bus cycle. BS 16 # must al-
ways meet setup and hold times
t17
and
t18
for cor-
rect operation.