Filter
Top Products
HARDWARE IMPLEMENTATION
cannot respond in two clocks can stretch the bus
cycle by holding READY inactive, that
is,
by
inserting wait states into the
cycle.
When running
back-to-back 32-bit bus cycles, the 80386's maxi-
mum bus bandwidth
is
32
megabytes per second
at
16
MHz
or
25
megabytes per second
at
12.5
MHz.
Due to its internal pipelining, the 80386 very
often knows the address and definition of the
next bus cycle before the external hardware
has responded to the current cycle. External
hardware can
use
the 80386's address pipelining
CLK2 [
(INPUT)
ADDRESS
AND [
DEFINITION
(OUTPUTS)
ADS
[
(OUTPUT)
NA[
(INPUT)
READY
[
(INPUT)
00-031
(INPUT [
DURING
READ)
CYCLE 1
(READ)
facility to gain early access to the following bus
cycle definition when it
is
available. Address
pipelining can give external hardware three
clock between address and data while main-
taining two-clock bandwidth to the processor.
Address pipelining
is
best exploited
by
interleaved
memory systems that can respond to accesses
in
alternate banks in parallel.
By
asserting Next
Address, the external hardware can ask the
80386 to output the next bus cycle definition as
soon as
it
is
available in the processor, rather
than waiting for READY (see Figure 5-6).
CYCLE 2
(READ)
CYCLE 3
(READ)
Figure
5-6.
Bus
Cycles
with
Pipelined
Addresses
5-6