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APPENDICES
A
Appendix 5 Processing Time
Appendix 5.3 Cyclic transmission delay time
(2) Standard communication
(a) Between the master station and an intelligent device station
• Master station (RX/RWr) Intelligent device station (input)
The following time is shown:
• The time between a signal input to the intelligent device station and the CPU module device of the master
station turning on or off
• The time between data input to the intelligent device station and the data being stored in the CPU module
device of the master station
SM : Master station sequence scan time
LS : Link scan time
n1 : SM LS (Round up the calculated value to the nearest integer.)
Rio : Intelligent device station processing time
( Manual for the intelligent device station used)
• Master station (RY/RWw) Intelligent device station (output)
The following time is shown:
• The time between the CPU module device of the master station turning on or off and the output of the
intelligent device station being turning on or off
• The time between data set to the CPU module device of the master station and the data output to the
intelligent device station
SM : Master station sequence scan time
LS : Link scan time
n2 : LS SM (Round up the calculated value to the nearest integer.)
Rio : Intelligent device station processing time
( Manual for the intelligent device station used)
Calculation
value
Block Data Assurance per Station No Block Data Assurance per Station
Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode
Normal value (SM × 1) + (LS × n1) + Rio (SM × 1) + (LS × 1) + Rio (SM × 1) + (LS × 1) + Rio (SM × 1) + (LS × 1) + Rio
Maximum
value
(SM × 1) + {LS × (n1 + 1)} + Rio (SM × 1) + (LS × 2) + Rio (SM × 1) + (LS × 2) + Rio (SM × 1) + (LS × 2) + Rio
Calculation
value
Block data assurance per station No block data assurance per station
Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode
Normal value (SM × n2) + (LS × 1) + Rio (SM × 1) + (LS × 1) + Rio (SM × 1) + (LS × 1) + Rio (SM × 1) + (LS × 1) + Rio
Maximum
value
(SM × n2) + (LS × 2) + Rio (SM × n2) + (LS × 1) + Rio (SM × 2) + (LS × 2) + Rio (SM × n2) + (LS × 1) + Rio