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Status and Event Reporting System
4–4
VX4101A MultiPaq Instrument User Manual
Table 4–1:
Instrument Operational Status Register (Cont.)
Bit # DescriptionName
6 ARMing Instrument is waiting for arm condition
7 CORRecting Instrument is performing a correction
8 Instrument Defined 0 Self-Test in progress
9 Instrument Defined 1 Abort in progress
10 Instrument Defined 2 Reserved by VX4101A
11 Instrument Defined 3 Reserved by VX4101A
12 Instrument Defined 4 Reserved by VX4101A
13 INSTrument summary Not used by VX4101A
14 PROGram running User-defined program is running
15 Reserved Always zero
The Instrument Operational Status Register structure appears in the above table.
An instrument uses this register during normal operation to record its current
state. As mentioned above, this register is composed of three subregisters and
two transition filters.
The Condition Register is updated by the instrument firmware in real-time. Bits
are set or cleared to identify what action the instrument is currently performing.
NOTE. The STATus:OPERational:CONDitional? query is described in the
individual instrument sections.
Note that some bits may not be used by some instruments and that there are five
bits which are instrument defined. See the individual instrument documentation
to determine which bits are used.
Following the condition register are two sets of transition filters. The Positive
Transition Filter is used to specify which bits of the Condition Register are only
of interest when they go from the Cleared to the Set state. The Negative
Transition Filter is also used to specify which bits of the Condition Register are
only of interest when they go from the Set to the Cleared state. For information
on any transition of a bit, both filters would be set.
Any transition which successfully passes through the transition filters sets the
corresponding bit in the event register. It is important to remember that for a bit
with the Negative Transition Filter set, a event in the Condition Register would
cause the same bit in the Event Register to be set, not cleared. Reading this
register causes it to be cleared.