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Status and Event Reporting System
4–6
VX4101A MultiPaq Instrument User Manual
The IEEE 488.2 Standard Event Status Register provides general status on the
VX4101 and all instruments and is at the same hierarchical level as the
VX4101A
Operational Status Register. Its structure is simpler than the operational status
register, in that the Condition Register and transition filters do not exist. This
register is cleared when read (by a *ESR? query) and when a *CLS command is
received. The register is eight bits wide as shown in the table below.
Table 4–3: Status Byte Register
Bit # Name Description
0 Operation Complete Set in response to *OPC?
1 Request Control Not Used by VX4101A
2 Query Error Error occurred during query
3 Device Specific Error Any error besides query, command or execution
4 Execution Error Error in command or query parameters
5 Command Error Command or query syntax error
6 User Request Not used by VX4101A
7 Power On Indicates initial power on condition
Table 4–4: IEEE 488.2 Standard Event Status Register
Bit # Name Description
0 Reserved Not Used by VX4101A
1 Reserved Not Used by VX4101A
2 Error/Event Queue Set when Error/Event Queue has one or more
entries
3 Questionable Summary Always zero
4 MAV Set when a message is available for a VXIbus read
5 ESR Summary Summary bit from IEEE 488.2 Standard Event
Status Register
6 MSS Master Summary Status
7 Operational Summary Summary bit from VX4101A Operational Status
Register
The summary bit from the IEEE 488.2 Standard Event Status Register propa-
gates to the IEEE 488.2 Status Byte Register. The IEEE 488.2 Standard Event
Status Enable Register is used to specify which events comprise the summary
bit.