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Glossary
Glossary–8
VX4101A MultiPaq Instrument User Manual
SYSFAIL*
A signal line on the VMEbus that is used to indicate a failure by a device.
The device that fails asserts this line.
System Clock Driver
A functional module that provides a 16 MHz timing signal on the Utility
Bus.
System Hierarchy
The tree structure of the commander/servant relationships of all devices in
the system at a given time. In the VXIbus structure, each servant has a
commander. A commander may also have a commander.
Test Monitor
An executive routine that is responsible for executing the self tests, storing
any errors in the ID-ROM, and reporting such errors to the Resource
Manager.
Test Program
A program, executed on the system controller, that controls the execution of
tests within the test system.
Test System
A collection of hardware and software modules that operate in concert to test
a target DUT.
TTLTRG
Open collector TTL lines used for inter-module timing and communication.
VXIbus Subsystem
One mainframe with modules installed. The installed modules include one
module that performs slot 0 functions and a given complement of instrument
modules. The subsystem may also include a Resource Manager.
Waveform Period
The waveform period is defined as the number of points in the waveform
times the sample period.
Word Serial Protocol
A VXIbus word oriented, bi-directional, serial protocol for communications
between message-based devices (that is, devices that include communication
registers in addition to configuration registers).
Word Serial Communications
Inter-device communications using the Word Serial Protocol.
WSP
See Word Serial Protocol.
10-MHz Clock
A 10 MHz, ±100 ppm timing reference. Also see CLK10.