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Status and Event Reporting System
VX4101A MultiPaq Instrument User Manual
4–5
Table 4–2: VX4101 A Operational Status Register
Bit # Name Description
1 Surepath Summary Summary bit from Surepath OSR
2 DMM Summary Summary bit from DMM OSR
3 Counter Summary Summary bit from Counter OSR
4 Instrument 4 Summary * Summary bit for Instrument 4
5 Instrument 5 Summary * Summary bit for Instrument 5
6 Instrument 6 Summary * Summary bit for Instrument 6
7 Instrument 7 Summary * Summary bit for Instrument 7
8 Instrument 8 Summary Summary bit for Instrument 8
9 Instrument 9 Summary Summary bit for Instrument 9
10 Instrument 10 Summary Summary bit for Instrument 10
11 Instrument 11 Summary Summary bit for Instrument 11
12 Instrument 12 Summary Summary bit for Instrument 12
13 Instrument 13 Summary Summary bit for Instrument 13
14 Instrument 14 Summary Summary bit for Instrument 13
15 Reserved Always zero
NOTE. Exact instrument N bit assignments will vary depending upon which of
the following optional devices are installed:
Digital to Analog Converter (DAC)
Digital Input
Digital Output
Relay Driver
The third register is the Event Enable Register. Bits are set or cleared in this
register to indicate which bits of the Event Register should be propagated to the
summary bit. The summary bit is the logical OR of each bit in the Event
Register logically ANDed with the corresponding bit in the Event Enable
Register. The summary bit becomes a single bit of another register in the next
level of the register hierarchy.
In the case of the
VX4101A, the next level in the hierarchy is the VX4101A
Operational Status Register. This register has the same structure as the Instru-
ment Operational Status Register with the following exception:
The summary bit of the
VX4101A Operational Status register propagates to a
bit in the IEEE 488.2 Status Byte Register.