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MEM module configuration
90
NS7520 Hardware Reference, Rev. D 03/2006
Memory Module Configuration register
Address: FFC0 0000
The Memory Module Configuration register (MMCR) defines basic MEM module
configurations.
Note:
The software reset command issued by the GEN module Software Service
register has no effect on any MEM Module Configuration registers.
Bits Access Mnemonic Reset Description
D31:24 R/W RFCNT 0 Refresh count value
Refresh period =
[(2*RFCNT + 2) * 2] / F
XTALE
Defines the refresh period for the memory
controller when FP/EDO DRAM or SDRAM is
being used. All DRAMs require a periodic
refresh cycle. You determine the specific
cycle.
Note: There is a small performance and
power penalty for programming a
refresh period smaller than
required.
The memory controller generates CAS
before RAS refresh cycles for all DRAM
types.
D23 R/W REFEN 0 Enable DRAM refresh
0 Disable DRAM refresh
1 Enable DRAM refresh
Must be set to 1 when DRAMs are used.
Table 36: MMCR bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
REFEN
RCYC A[27] A[26]
AMUX
2
RFCNT
Reserved
AMUX A[25]