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Working with the CPU
Hardware Interrupts
Two wires that go into the ARM7 CPU core can interrupt the processor:
IRQ (normal interrupt)
FIRQ (fast interrupt)
Although the interrupts are basically the same, FIRQ can interrupt IRQ.
FIRQ and IRQ lines
The FIRQ line adds a simple, two-tier priority scheme to the interrupt system. Most
sources of interrupts on the ARM7TDMI come from the IRQ line. The only potential
sources for FIRQ interrupts in the ARM7TDMI come from the two built-in timers and
the watchdog timer; there is no way to generate an FIRQ signal externally. These
timers are controlled by registers in the GEN module (see "Timer Control registers,"
beginning on page 70):
The built-in timers are controlled using the Timer Control registers
(’hFFB0 0010/18). The corresponding bit in the Interrupt Enable register
must be set for either IRQ or FIRQ to function.
The watchdog timer is controlled using the System Control register
(’hFFB0 0000).
Interrupt controller
Interrupts come from many different sources on the ARM7TDMI, and are managed by
the interrupt controller within the GEN module. Interrupts can be enabled or disabled
on a per-source basis using the Interrupt Enable register (’hFFB0 0030), which serves
as a mask for the interrupt sources and ultimately controls whether an interrupt from
an ARM7TDMI module can reach the IRQ line.
There are two read-only registers in the interrupt controller:
Interrupt Status Register Raw. Indicates the source of an ARM7TDMI
interrupt regardless of the state of the Interrupt Enable register. All
interrupts that are active in their respective module will be visible in the
Interrupt Status Register Raw.