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DMA channel assignments
156
NS7520 Hardware Reference, Rev. D 03/2006
DMA channel assignments
One DMA channel is dedicated to Ethernet receive and one DMA channel is dedicated
to Ethernet transmit. The Ethernet receiver has four DMA subchannels, which support
the receive buffer descriptor selection feature (see "DMA buffer descriptor,"
beginning on page 130).
The Ethernet receiver is assigned DMA channel 1 (1A, 1B, 1C, and 1D).
The Ethernet transmitter is assigned DMA channel 2.
EFE configuration
Table 52 shows the Ethernet front-end register map. All registers are 32 bits unless
otherwise noted.
Note:
Reading or writing the MAC configuration registers (address locations
0xFF80 0400 through 0xFF80 05DC) is unreliable without valid clocks on
the TXCLK and RXCLK input pins.
Address Register Register description
FF80 0000 EGCR Ethernet General Control register
FF80 0004 EGSR Ethernet General Status register
FF80 0008 FIFO Ethernet FIFO Data register
FF80 000C FIFOL Ethernet FIFO Data Register Last
FF80 0010 ETSR Ethernet Transmit Status register
FF80 0014 ERSR Ethernet Receive Status register
FF80 0400 MAC1 MAC Configuration Register 1
FF80 0404 MAC2 MAC Configuration Register 2
FF80 0408 IPGT Back-to-Back Inter-Packet-Gap register
FF80 040C IPGR Non-Back-to-Back Inter-Packet-Gap register
FF80 0410 CLRT Collision Window/Retry register
Table 52: EFE register map