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Ethernet transmitter considerations
144
NS7520 Hardware Reference, Rev. D 03/2006
Ethernet transmitter considerations
When the DMA for an Ethernet transmit frame completes and the F bit is set in the
buffer descriptor, the packet transmission starts immediately no matter the value in
the watermark field. If the F bit is clear, packet transmission is delayed until the FIFO
contains the same number of bytes as the selected watermark. See "Ethernet General
Control register (EGCR) bit definitions" on page 158 for more information.
D20 R/W CAIE 0 Channel abort interrupt enable
Use these bits to enable interrupts to be generated
when the associated IP bits are set.
In general, the NCIE bit is used for inbound
(write DMA) operations.
The DMA buffer descriptor I bit should be
used for outbound (read DMA) operations.
The ECIE and CAIE bits should always be
enabled.
NCIE and the DMA buffer descriptor I bit
should not be used at the same time.
D19 R WRAP 0 Last descriptor in descriptor list
D18 R IDONE 0 Interrupt on done
D17 R LAST 0 Last buffer descriptor in current data frame
D16 R FULL 0 Buffer full indicator
D15 N/A Reserved N/A N/A
D[14:00] R BLEN 0 Remaining byte transfer count
Use these bits for debugging purposes only. The
bits serve no useful purpose to the firmware device
driver.
Bits Access Mnemonic Reset Description
Table 51: DMA Status/Interrupt Enable register bit definition