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DMA Module
Figure 20: Hardware needed for external memory-to-memory DMA transfers
If the source buffer pointer points to the external device, the device, in
conjunction with appropriate memory device timing or external bus cycle
timing, provides data when DACK_ is asserted.
If the destination buffer pointer points to the external device, the device,
in conjunction with appropriate memory device timing or external bus cycle
timing, accepts data when DACK_ is asserted.
TEA_ indicates the existence and termination of burst cycles.
DMA controller reset
You can simultaneously reset the DMA controllers for channels 1-13 without affecting
any NS7520 modules. Just set the DMA reset bit in the GEN module System Control
register to 1 and then back to 0 (see "DMARST" on page 67).
All DMA controllers are reset by all forms of hardware and software resets.
Memory
NS7520
External device
DREQ_
Enable
DONE
Direction
DATA[31:0]
ADDR[27:0]
CS
DREQ_
DACK_
DONE_
R/W_
DATA[31:0]
ADDR[27:0]
CSx_
CSx_
CS_
ADDR[X:0]
DATA{31:0]
R/W_