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EFE configuration
178
NS7520 Hardware Reference, Rev. D 03/2006
MAC Configuration Register 1
Address: FF80 0400
MAC Configuration Register 1 contains bits that control functionality within the
Ethernet MAC block.
D05 R ROVER 0 Receive overflow
Set to 1 to indicate that a receive FIFO overrun
condition has occurred.
An overrun condition occurs when the FIFO
becomes full while receiving an Ethernet packet.
This condition indicates that the DMA controller
was not able to empty the FIFO at a fast enough
rate compared to the rate that information was
received from the Ethernet medium for one of
these reasons:
The DMA controller was not configured for
bursting.
The memory peripheral device was not
configured for bursting.
The memory peripheral device is too slow to
support the Ethernet interface.
When this bit is set, the RXREGR and RXFIFOH bits
in the Ethernet General Status register remain
inactive. The bad receive packet is flushed
immediately from the FIFO.
D04:00 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 59: Ethernet Receive Status register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
SRST
SIM
RST
Reserved
RPEM
CSR
RPER
FUN
RPEM
CST
RPET
FUN
Reserved
LOOP
BK
TX
FLOW
RX
FLOW
PALL
RX
RXEN