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Serial Channel registers
248
NS7520 Hardware Reference, Rev. D 03/2006
D22 R/W RXCINV 0 Receive clock invert
0 Normal; RXD sampled on rising edge of RX
clock
1 Inverted; RXD sampled on falling edge of
RX clock
Controls the relationship between receive
clock and receive data.
When set to 0, receive data input is
sampled at the low-to-high transition of
the receive clock.
When set to 1, receive data input is
sampled at the high-to-low transition of
the receive clock.
Note: When using SPI mode, this bit must
be set to zero.
D21 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 90: Serial Channel Bit-Rate register bit definition