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Setting the PLL frequency
56
NS7520 Hardware Reference, Rev. D 03/2006
18.4 01 01 11 00 10111 00100 0x00000003
23.0 00 01 11 00 10000 00101 0x00000084
27.6 00 01 11 00 10001 00110 0x00000085
32.3 00 01 11 00 10010 00111 0x00000086
36.9 00 10 11 00 10011 01000 0x00000087 1
41.5 11 10 11 00 11100 01001 0X00000108
46.1 11 10 11 00 11101 01010 0x00000109 2
50.7 11 10 11 00 11110 01011 0x0000010A
55.3 11 10 11 00 11111 01100 0x0000010B 3, 4
59.9 11 10 11 00 11000 01101 0x0000010C
64.5 11 10 11 00 11001 01110 0x0000010D
69.1 11 10 11 00 11010 01111 0x0000010E
73.7 11 11 11 00 11011 10000 0x0000010F
78.3 10 11 11 00 00100 10001 0X00000190
82.9 10 11 11 00 00101 10010 0x00000191
87.6 10 11 11 00 00110 10011 0x00000192
92.2 10 11 11 00 00111 10100 0x00000193
96.8 10 11 11 00 00000 10101 0x00000194
101.4 10 11 11 00 00001 10110 0x00000195
106.0 10 11 11 00 00010 10111 0x00000196
110.6 10 11 11 00 00011 11000 0x00000197
115.2 10 11 11 00 01100 11001 0x00000198
119.8 10 11 11 00 01101 11010 0x00000199
124.4 10 11 11 00 01110 11011 0X0000019A
129.0 10 11 11 00 01111 11100 0X0000019B
133.6 10 11 11 00 01000 11101 0X0000019C
138.2 10 11 11 00 01001 11110 0X0000019D
142.8 10 11 11 00 01010 11111 0X0000019E
MHz A[8:7] IS A[6:5] FS A[4:0] ND+1 PLL Settings reg Notes