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Serial Controller Module
D03 R TRDY 0 Transmit register empty interrupt pending
Indicates data can be written to the FIFO Data
register. TRDY typically is used only in
interrupt-driven applications; it is not used for
DMA operation. The TRDY status condition
can be programmed to generate an interrupt
by setting the related IE bit in Serial Channel
Control Register A.
TRDY is never active while the TBC bit is
active. TBC must be acknowledged to activate
the TRDY bit. When the transmitter is
configured to operate in DMA mode, the
interlock between TBC and TRDY is handled
automatically in hardware.
D02 R THALF 0 Transmit FIFO half-empty interrupt pending
Indicates that the transmit data FIFO contains
room for at least 16 bytes. The THALF field
typically is used only in interrupt-driven
applications; it is not used for DMA operation.
The THALF status condition can be
programmed to generate an interrupt by
setting the related IE bit in Serial Channel
COntrol Register A.
D01 R/C TBC 0 Transmit buffer closed interrupt pending
Indicates a transmit buffer closed condition.
Once set, the TBC bit remains set until
acknowledged. TBC is acknowledged by
writing a 1 to this same bit position in this
register. The TBC bit is acknowledged
automatically by hardware when the
transmitter is configured to operate in DMA
mode. The TBC status condition can be
programmed to generate an interrupt by
setting the related IE bit in Serial Channel
Control Register A.
Bits Access Mnemonic Reset Description
Table 89: Serial Channel Status Register A bit definition