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143
DMA Module
D29 R/C NRIP 0 Buffer not ready interrupt pending
Set when the DMA channel encounters a buffer
descriptor whose F bit is in the incorrect state.
When NRIP is set, the DMA channel stops until the
bit is cleared by firmware; the DMA channel does
not go to the next buffer descriptor.
When NRIP is cleared by firmware, the buffer
descriptor is tried again.
D28 R/C CAIP 0 Channel abort interrupt pending
Set when the DMA channel finds that the CA bit is
set in the DMA Control register. When CAIP is set,
the DMA channel stops until the bit is cleared by
firmware. The DMA channel automatically goes to
the next buffer descriptor when CAIP is cleared.
The CA bit in the DMA Control register must be
cleared, using firmware, before CAIP is cleared.
Otherwise, the next buffer descriptor aborts as
well.
D27 R/C PCIP 0 Premature complete interrupt pending
Set when the DMA channel, configured to operate
in fly-by read mode, receives an end-of-transfer
indicator from the peripheral while processing a
DMA buffer descriptor. The DMA channel goes to
the next buffer descriptor.
NCIP is set when PCIP is set, for backward
compatibility.
D26:25 N/A Reserved N/A N/A
D24 R/W PCIE 0 Premature complete interrupt enable
D23 R/W NCIE 0 Normal completion interrupt enable
D22 R/W ECIE 0 Error completion interrupt enable
D21 R/W NRIE 0 Buffer not ready interrupt enable
Bits Access Mnemonic Reset Description
Table 51: DMA Status/Interrupt Enable register bit definition