Filter
Top Products
EFE configuration
158
NS7520 Hardware Reference, Rev. D 03/2006
Ethernet General Control register (EGCR) bit definitions
Address: FF80 0000
General information
These fields should be set only once, on device open:
These fields are used only when using Ethernet receive in interrupt service mode
rather than DMA mode (DMA interface logic). DMA mode provides higher performance
out of the Ethernet chip, and can be turned on and off.
Register bit assignment
Note:
Bits D15:D00 are media control bits, with D07:D00 used in ENDEC mode
only.
ERX ETX
ERXDMA ETXDMA
ERXLNG ETXWM
ERXSHT EFULLD
ERXBAD
ERXREG ETXREG
ERFIFOH ETFIFOH
ERXBR ETXBC
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
ERX
LNG
ETX ETXWM
ERX
PDN:, AUI_TP:, LNK_DIS:, LPBK:, UTP_STP
ERX
DMA
ETX
DMA
ERX
SHT
ERX
REG
MODE
ERX
BAD
ETX
REG
ET
FIFOH
ETX
BC
E
FULLD
ER
FIFOH
ERX
BR
Rsvd
RXC
INV
TXC
INV
pNA
MAC_
RESET
ITXA EXINT