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EFE configuration
196
NS7520 Hardware Reference, Rev. D 03/2006
MII Management Read Data register
Address: FF80 0430
Register bit assignment
Bits Access Mnemonic Reset Description
D31:16 N/A Reserved N/A N/A
D15:00 R MRDD N/A MII read data
Provides read data following an MII management
read cycle.
An MII management read cycle is executed by
loading the PHY Address register, then setting the
READ bit in the MII Indicators register (see
page 197) to 1. Read data is available after the
BUSY bit in the MII Indicators register returns to 0.
Table 74: MII Management Read Data register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
MII read data