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Working with ARM exceptions
38
NS7520 Hardware Reference, Rev. D 03/2006
Note:
An explicit switch back to Thumb state is never needed. Restoring the
CPSR from the SPSR automatically sets the T bit to the value it held
immediately before the exception.
Exception entry/exit summary
In the variable
R14_x, R14 is the Link register; _x is the previous state of the
processor.
Notes:
1
Where PC is the address of the BL/SWI/undefined instruction fetch that had the
prefetch abort. BL is a branch with link instruction.
2 Where PC is the address of the instruction that was not executed since FIRQ or
IRQ took priority.
3 Where PC is the address of the load or store instruction that generated the data
abort.
4 The value saved in R14_svc upon reset is unpredictable.
Return/
exception Return instruction
Previous state
ARM R14_x
Previous state
Thumb R14_x Notes
BL
MOV PC, R14
PC+4 PC+2 1
RESET NA NA NA 4
UNDEF
MOVS PC, R14_und
PC+4 PC+2 1
SWI
MOVS PC, R14_svc
PC+4 PC+2 1
ABORT P
SUBS PC, R14_abt, #4
PC+4 PC+4 1
ABORT D
SUBS PC, R14_abt, #8
PC+8 PC+8 3
IRQ
SUBS PC, R14_irq, #4
PC+4 PC+4 2
FIRQ
SUBS PC, R14_firq, #4
PC+4 PC+4 2
Table 18: Exception entry/exit by exception type