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Setting the PLL frequency
54
NS7520 Hardware Reference, Rev. D 03/2006
Setting the PLL frequency
Three fields — IS (charge pump current), FS (output divider), and ND (PLL
multiplier) — in the PLL Settings register control the behavior of the PLL circuit. You
cannot write to the PLL Settings register directly, however; it is configured in one of
these ways:
1 On bootup, the PLL Settings register is configured by reading the values on
address lines A[8:0]. The address lines have internal pullups. The normally high
values can be changed to 0 by connecting 2.7K pulldown resistors.
2 The PLL Settings register is configured by writing to the PLL Control register.
Only the ND field can be reconfigured this way.
PLL Settings register: Setting the PLL frequency on bootup
The PLL Settings register, FFB0 0040, is initialized at bootup by reading address lines
A[8:0]. Only the ND field can be changed by writing a new bus speed to the PLLCNT
register in the PLL Control register.
Bits Access Mnemonic Reset Description
D31:09 N/A Reserved N/ N/A
Table 21: PLL Settings register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
IS
Reserved FS ND