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Index-8
SDRAM timing 281
-
288
Serial Channel 1,2 Bit-Rate registers 244
Serial Channel 1,2 Control Register A 225
receiver interrupts 229
transmitter interrupts 230
Serial Channel 1,2 Control Register B 231
Serial Channel 1,2 FIFO registers 254
Serial Channel 1,2 Receive Buffer Gap
Timer 255
Serial Channel 1,2 Receive Character Gap
Timer 256
Serial Channel 1,2 Receive Match MASK
register 258
Serial Channel 1,2 Receive Match
register 258
Serial Channel 1,2 Status Register A 235
serial internal/external timing 303
-
304
serial interrupts 40
serial module 209
-
259
and bit-rate generator 211
configuration 223
features 210
GPIO configurations 222
protocols 212
receiver interrupt enable bits 229
Serial Channel 1,2 Bit-Rate
registers 244
Serial Channel 1,2 Control
Register A 225
Serial Channel 1,2 Control
Register B 231
Serial Channel 1,2 FIFO registers 254
Serial Channel 1,2 Receive Buffer Gap
Timer 255
Serial Channel 1,2 Receive Character
Gap Timer 256
Serial Channel 1,2 Receive Match MASK
register 258
Serial Channel 1,2 Receive Match
register 258
Serial Channel 1,2 Status
Register A 235
serial port performance 223
SPI mode 213
-
222
FIFO management 214
master mode 217
-
219
receive FIFO interface 215
slave mode 219
-
222
transmit FIFO interface 214
structure 211
transmitter interrupt enable bits 230
UART mode 212
-
213
serial port performance 223
serial ports 3
single data transfer instructions 35
SMII Status register 198
software action 37
software reset circuit source 59
Software Service register 70
SPI 213
-
222
controller features 213
FIFO management 214
master configuration 213
master mode 217
-
219
configuration 217
receiver 219
signals 217
transmitter 218
slave configuration 213
slave mode 219
-
222
configuration 220
receiver 221
signals 220
transmitter 221
SRAM controller 102
-
105
burst cycles 104