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Serial Controller Module
Serial port performance
The serial ports have a finite performance limit on their ability to handle various
serial protocols. Performance is limited by the speed of the SYSCLK operating the
NS7520. The configured speed for the internal PLL defines the SYSCLK rate, as shown
in this table:
Configuration
The serial controller module has a block of configuration space as shown:
Operating Mode Serial Port Maximum Rate
UART (x16) SYSCLK/64
UART (x1) SYSCLK/4
SPI SYSCLK/8
Address Register
FFD0 0000 Channel 1 Control Register A
FFD0 0004 Channel 1 Control Register B
FFD0 0008 Channel 1 Status Register A
FFD0 000C Channel 1 Bit-Rate register
FFD0 0010 Channel 1 FIFO Data register
FFD0 0014 Channel 1 Receive Buffer Gap Timer
FFD0 0018 Channel 1 Receive Character Gap Timer
FFD0 001C Channel 1 Receive Match register
FFD0 0020 Channel 1 Receive Match Mask register
FFD0 0040 Channel 2 Control Register A
FFD0 0044 Channel 2 Control Register B
FFD0 0048 Channel 2 Status Register A