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Pinout detail tables and signal descriptions
16
NS7520 Hardware Reference, Rev. D 03/2006
Chip select controller
The NS7520 supports five unique chip select configurations:
TA_ Transfer acknowledge Indicates the end of the current system bus
memory cycle. This signal is driven to 1 prior to
tri-stating its driver.
TA_ is bi-directional.
TEA_ Transfer error
acknowledge
Indicates an error termination or burst cycle
termination:
In conjunction with TA_ to signal the end of a
burst cycle.
Independently of TA_ to signal that an error
occurred during the current bus cycle. TEA_
terminates the current burst cycle.
This signal is driven to 1 prior to tri-stating its
driver.
TEA_ is bi-directional. The NS7520 or the external
peripheral can drive this signal.
RW_ Read/write indicator Indicates the direction of the system bus memory
cycle. RW_ high indicates a read operation; RW_
low indicates a write operation. The RW_ signal is
bi-directional.
BR_ Bus request NO CONNECT
BG_ Bus grant NO CONNECT
BUSY_ Bus busy NO CONNECT
Mnemonic Signal Description
Table 3: System bus interface signal description
Symbol Pin I/O OD Description
CS4_ B4 O 4 Chip select/DRAM RAS_
CS3_ A4 O 4 Chip select/DRAM RAS_
CS2_ C5 O 4 Chip select/DRAM RAS_
CS1_ B5 O 4 Chip select/DRAM RAS_
Table 4: Chip select controller pinout