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Hardware Interrupts
40
NS7520 Hardware Reference, Rev. D 03/2006
Interrupt Status Register Enabled. Identifies the current state of all
interrupt sources that are enabled. This register is defined by performing a
logical AND of the Interrupt Status Register Raw and the Interrupt Enable
register. All bits in the Interrupt Status Register Enabled are ORed together.
The output is fed directly to the IRQ line, which then interrupts the ARM.
Interrupt sources
Each interrupt source is enabled and disabled within its respective module (and
submodule) within the NS7520 ASIC. The interrupt controller in the GEN module,
however, does not latch any of the interrupt signals.
Note:
Interrupt causes are latched in their respective submodule until cleared.
Interrupt sources include the following:
DMA interrupts. All [13] DMA channels, including the four sub-channels of
the Ethernet receiver, have five possible interrupt sources. See Chapter 8,
"DMA Module."
Ethernet receive and transmit interrupts. There are three interrupts for
Ethernet receive and four interrupts for Ethernet transmit; all interrupts
are part of the Ethernet General Status register. These interrupts are used
only when the Ethernet receiver and transmitter are in interrupt mode
rather than DMA mode. See Chapter 9, "Ethernet Module."
Serial interrupts. The Serial Channel Status register has many interrupt
sources. See Chapter 10, "Serial Controller Module."
Watchdog timer interrupts. When the watchdog timer expires, the system
can generate either an IRQ interrupt, an FIRQ interrupt, or a system reset.
The interrupt type and length of the timer are configured using the GEN
module System Control register. The watchdog is strobed using the Software
Service register. See Chapter 6, "GEN Module."
Timer 1 and Timer 2 interrupts. Two types of interrupts can be generated
by Timers 1 and 2. The interrupt type is configured in the Timer Control
register; the interrupt itself is contained within the Timer Status register.
See Chapter 6, "GEN Module."