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Memory Controller Module
Figure 14: SDRAM burst write
The precharge command is issued, when necessary, during the T1 phase of a
normal or burst write cycle. The precharge command is issued only when
the row selection for the chip select has changed since the last address.
Each chip select maintains a 14-bit register identifying the last row
accessed. Additional clock cycles are inserted between the precharge
command and the active command, depending on the WAIT configuration.
The active command is always issued after the precharge command. The
active command selects a newly activated row address. Additional clock
cycles are inserted between the active command and the read command,
depending on the WAIT configuration.
One Valid Per Cycle
writewrite write write nop inhi bi tnop
BCLK
TS_
RW_
BE[3:0]
D[31:0]
CS[7:0]_
CAS3_(RAS_)
CAS2_(CAS_)
CAS1_(WE_)
A[13:0]
AMUX
TA_ {output}
TEA_(LAST_) {output}
TA_ {input}
TEA_(LAST_) {input}