Filter
Top Products
EFE configuration
168
NS7520 Hardware Reference, Rev. D 03/2006
The transmit FIFO has a secondary address (FF80 000C) that signifies the last word of
a transmit frame. The first and middle words must use the primary address
(FF80 0008).
Writing to the secondary address with the transmit interrupts disabled (ETXBC in the
Ethernet General Control register) initiates transmission of data from the transmit
FIFO. Otherwise, transmission begins when the TX FIFO byte count equals the
selected watermark (ETXWM in the Ethernet General Control register).
Reading from the Ethernet FIFO Data register
Reading from the Ethernet FIFO Data register empties the receive FIFO. The Ethernet
General Status register indicates how many bytes are available to be read. The
receive FIFO is available only when the RXBR bit has been set to 1, which clears the
bit, in the Ethernet General Status register.
Note:
The Ethernet Receive Status register (see "Ethernet Receive Status
register" on page 174) should be read before clearing the RXBR bit. When
operating in interrupt service mode, RXBR is cleared manually. When
operating in DMA mode, the Ethernet Receive Status register is read
automatically and RXBR is cleared automatically.
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
FIFO data: first and middle words
FIFO data: first and middle words
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
FIFO data: last word
FIFO data: last word