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Serial Channel registers
238
NS7520 Hardware Reference, Rev. D 03/2006
D21:20 R RXFDB 0 Receive FIFO data available
00 Full-word
01 One byte
10 Half-word
11 Three bytes (LENDIAN determines which
three)
Identifies the number of valid bytes contained
in the next long word to be read from the Serial
Channel FIFO Data register. The next read of
the FIFO can contain one, two, three, or four
valid bytes of data. This field must be read
before the FIFO is read, to determine which
bytes of the 4-byte long word contain valid
data.
Normal Endian byte-ordering rules apply to the
Serial Channel FIFO Data register.
D19 R DCD 0 Current data carrier detect state
0Inactive
1Active
Identifies the current state of the EIA data
carrier detect signal.
D18 R RI 0 Current ring indicator state
0Inactive
1Active
Indicates the current state of the EIA ring
indicator signal.
D17 R DSR 0 Current data set ready state
0Inactive
1Active
Indicate the current state if the EIA data set
ready signal.
D16 R CTS 0 Current clear to send state
0Inactive
1Active
Identifies the current state of the EIA clear to
send signal.
Bits Access Mnemonic Reset Description
Table 89: Serial Channel Status Register A bit definition