Filter
Top Products
EFE configuration
184
NS7520 Hardware Reference, Rev. D 03/2006
Back-to-Back Inter-Packet-Gap register
Address: FF80 0408
Register bit assignment
Bits Access Mnemonic Reset Description
D31:07 N/A Reserved N/A N/A
D06:00 R/W IPGT N/A Back-to-back inter-packet-gap
A programmable field that represents the nibble
time offset of the minimum possible period
between the end of any transmitted packet to the
beginning of the next packet.
Full-duplex mode. The register value should be
the proper period in nibble times minus 3.
The recommended setting is
’h15 (21d),
which represents these minimum IPG values:
— In 100 Mbps: 0.96 μs
— In 10 Mbps: 9.6 μs
Half-duplex mode. The register value should
be the proper period in nibble times minus 6.
The recommended setting is
’h12 (18d),
which represents these minimum IPG values:
— In 100 Mbps: 0.96 μs
— In 10 Mbps: 9.6 μs
Table 63: Back-to-Back Inter-Packet-Gap register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
IPGTReserved