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71
GEN Module
timer can be programmed to generate an interrupt to the CPU. The CPU can read the
current count value (CTC) at any time.
These equations determine the timeout interval:
TIMEOUT = [8 * (TC + 1)] / F
XTALE
TCLK = 0; TPRE = 0
TIMEOUT = [4096 * (TC + 1)] / F
XTALE
TCLK = 0; TPRE = 1
TIMEOUT = (TC + 1) / F
SYSCLK
TCLK = 1; TPRE = x
Register bit definition
Bits Access Mnemonic Reset Description
D31 R/W TE 0 Timer enable
1 Allows the timer to operate.
0 Resets and disables the timer.
The other fields in this register should be
configured before or during the same memory
cycle in which TE is set to 1.
D30 R/W TIE 0 Timer interrupt enable
When set to 1, allows the timer to interrupt the
CPU. A timer interrupt is generated when the
hardware sets the TIP bit in the Timer Status
register (see "Timer Status registers" on page 73).
D29 R/W TIRO 0 Timer interrupt mode
0 Normal interrupt
1 Fast interrupt
Controls the type of interrupt the timer asserts to
the CPU.
Table 27: Timer Control registers bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
TE TIE TIRO TPRE TCLK ITC
ITC