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DMA channel registers
134
NS7520 Hardware Reference, Rev. D 03/2006
DMA channel registers
All registers are 32-bit unless otherwise noted.
Address map
The next table sows the address map for the DMA channel configuration registers.
The DMA Control register should be written to enable the DMA channel only after all
other registers and descriptors are valid.
Address Description
FF90 0000 DMA 1 “A” Buffer Descriptor Pointer register
FF90 0010 DMA 1 “A” Control register
FF90 0014 DMA 1 “A” Status register
FF90 0020 DMA 1 “B” Buffer Descriptor Pointer register
FF90 0030 DMA 1 “B” Control register
FF90 0034 DMA 1 “B” Status register
FF90 0040 DMA 1 “C” Buffer Descriptor Pointer register
FF90 0050 DMA 1 “C” Control register
FF90 0054 DMA 1 “C” Status register
FF90 0060 DMA 1 “D” Buffer Descriptor Pointer register
FF90 0070 DMA 1 “D” Control register
FF90 0074 DMA 1 “D” Status register
FF90 0080 DMA 2 Buffer Descriptor Pointer register
FF90 0090 DMA 2 Control register
FF90 0094 DMA 2 Status register
FF90 00A0 DMA 3 Buffer Descriptor Pointer register
FF90 00B0 DMA 3 Control register
FF90 00B4 DMA 3 Status register
FF90 00C0 DMA 4 Buffer Descriptor Pointer register
FF90 00D0 DMA 4 Control register