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Timing Diagrams
292
NS7520 Hardware Reference, Rev. D 03/2006
FP DRAM write
Fast Page write
Notes:
1 If the next transfer is DMA, null periods between memory transfers can occur.
Thirteen clock pulses are required for DMA context switching.
2 Port size determines which byte enable signals are active:
– 8-bit port = BE3*
– 16-bit port = BE[3:2]
– 32-bit port = BE[3:0]
3 Port size determines which CAS signals are active:
– 8-bit port = CAS3*
– 16-bit port = CAS[3:2]
– 32-bit port = CAS[3:0]
4 The TA* and TEA*/LAST signals are for reference only.
T1 TW T2 Note-1 T1
12
3737
4343
2727
2929
139
35
6
3636
3131
3030
15
14
Note-2
Note-3
BCLK
TA* (Note-4)
TEA*/LAST (Note-4)
TA* (input)
BE[3:0]*
Non-muxed address
Muxed address
write D[31:0]
WE*
(FP)RAS[4:0]*
(FP)CAS[3:0]*
PortA2/AMUX
RW*