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Serial Channel registers
258
NS7520 Hardware Reference, Rev. D 03/2006
Serial Channel 1,2 Receive Match register
Address: FFD0 001C / 5C
When the serial channel is configured for UART mode, the Receive Match register
provides the data bytes that the receiver uses to compare against the incoming
receive data stream. If a match is found and the appropriate match enable bit is set
in Serial Channel Control Register B, the current receive data buffer is closed by the
serial channel and a new buffer is started.
In UART configurations, individual bits within the match register bytes can be masked
using the Receive Match MASK register (see "Serial Channel 1, 2 Receive Match MASK
register" on page 258).
Register bit assignment
Serial Channel 1, 2 Receive Match MASK register
Address: FFD0 0020 / 60
The Receive Match MASK register masks those bits in the Receive Match Data register
that should not be included in the match comparison. To mask a bit in the match
comparison function, place a 1 in the same bit position in this register.
Bits Access Mnemonic Reset Description
D31:24 R/W RDMB1 0 Receive data match byte 1
D23:16 R/W RDMB2 0 Receive data match byte 2
D15:08 R/W RDMB3 0 Receive data match byte 3
D07:00 R/W RDMB4 0 Receive data match byte 4
Table 94: Serial Channel Receive Match register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
RDMB1 RDMB2
RDMB3 RDMB4