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EFE configuration
174
NS7520 Hardware Reference, Rev. D 03/2006
Ethernet Receive Status register
Address: FF80 0014
The Ethernet Receive Status register contains the status for the last completed
receive buffer. The receive buffer complete bit (RXBR) is set in the Ethernet General
Status register when a receive frame is completed and the Receive Status register is
loaded. The lower 16 bits (D15:00) of the register are also loaded into the
StatusOrIndex field of the DMA buffer descriptor when using DMA mode.
D03:00 R TXCOLC 0 Transmit collision count
Indicates how many collisions the MAC
encountered while it was trying to transmit the
package. TXCOLC indicates only that collision
events have occurred; if the packet transmission
was aborted, the TXAEC bit will be set.
The MAC tries to retransmit the packet up to the
maximum number of collision retries defined by the
RETRY field in the Collision Window/Collision Retry
register.
This bit is valid (1) when the TXAL or TXAEC bits
are set; otherwise, the bit is set to 0.
Bits Access Mnemonic Reset Description
Table 58: Ethernet Transmit Status register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
RXSIZE
RX
LNG
ReservedRXCE RXDV RXOK RXBR RXMC
RX
CRC
RXDR
RXCV
RX
SHT
ROVER