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Serial Channel registers
228
NS7520 Hardware Reference, Rev. D 03/2006
D17 R/W DTR 0 Data terminal ready active
Controls the state of the external data terminal
ready signal.
Setting DTR to 1 causes the DTR output
to go active.
Setting DTR to 0 causes the DTR output
to go inactive.
D16 R/W RTS 0 Request-to-send active
Controls the state of the external request-to-
send signal.
Setting RTS to 1 causes the RTS output
to go active.
Setting RTS to 0 causes the RTS output
to go inactive.
D15:09 R/W IE 0 Receiver interrupt condition
The interrupt enable bits are used to enable an
interrupt when the respective status bit is set
in Serial Channel Status A.
Setting the IE field to 1 enables the
interrupt.
Setting the IE field to 0 disables the
interrupt.
Table 86, “Receiver interrupt enable bits,” on
page 229, lists individual bit numbers and
descriptions.
D08 R/W ERXDMA 0 Enable receive DMA requests
Enables the receiver to interact with a DMA
channel. When configured to operate in DMA
mode, the DMA controller empties the receive
data FIFO and delivers the data to memory.
The receive status information from Serial
Status registers B and C automatically moves
to the receive DMA buffer descriptor.
Clear this bit to pause the receiver.
Bits Access Mnemonic Reset Description
Table 85: Serial Channel Control Register A