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DMA channel registers
140
NS7520 Hardware Reference, Rev. D 03/2006
REQ continued DMA channels 4/6 interface with an external
peripheral using handshaking signals multiplexed
through PORTC.
When REQ is set to 0 in DMA channel 4 and
set to 1 in DMA channel 6, DMA channel 6 is
tied to the external DMA port through PORTC.
When REQ is set to 1 in DMA channel 4, that
channel is tied to the external DMA port
through PORTC, no matter the REQ bit setting
in DMA channel 6.
These bits should not be set in any channels other
than DMA 3, 4, 5, or 6.
D22 N/A Reserved N/A N/A
D21 R/W SINC_ 0 Source address increment
0 Increment source address pointer
1 Do not increment source address pointer
Controls whether the source address pointer is
incremented after each DMA transfer. The DMA
controller uses this bit in all modes when referring
to a memory address. This bit is ignored when the
source is a fly-by port.
D20 R/W DINC_ 0 Destination address increment
0 Increment destination address pointer
1 Do not increment destination address pointer
Controls whether the destination address pointer is
incremented after each DMA transfer. The DMA
controller uses this bit in all modes when referring
to a memory address. This bit is ignored when the
destination is a fly-by port.
For memory-to-memory operation with
DINC_=0,
the data is written to the specified destination
address and all subsequent data are written are
written to the specified destination address+4.
D19:18 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 50: DMA Control register bit definition